1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to incorporating silicon atoms into a high K dielectric using gas cluster ion beam implantation. The high K dielectric is annealed to form silicon dioxide from the silicon atoms to enhance the quality of the high K dielectric.
2. Description of the Related Art
Various devices within an integrated circuit employ a gate dielectric interposed between two layers composed of semiconductive or conductive materials. For example, the gate dielectric may be interposed between a polycrystalline silicon ("polysilicon") gate conductor and a silicon-based substrate in a well-known MOSFET transistor device. The gate dielectric may also be placed between a polysilicon control gate and a polysilicon floating gate in a well-known FLOTOX EEPROM memory device. The gate dielectric of a circuit device serves to isolate the overlying and underlying materials while also permitting capacitive coupling between those materials.
It has been necessary to increase the capacitances of integrated circuit devices in order to meet the high demand for faster and more complex circuits. The capacitance is dependent upon the thickness of the gate dielectric and the relative permittivity of the gate dielectric. Decreasing the thickness of the gate dielectric gives rise to an increase in the capacitance. Permittivity, .epsilon., of a material reflects the ability of the material to be polarized by an electric field. Therefore, capacitance between two layers of conductive material separated by a dielectric is directly proportional to the permittivity of the dielectric. The permittivity of a material is typically described as its permittivity normalized to the permittivity of a vacuum, .epsilon..sub.0. Hence, the relative permittivity or dielectric constant, K, of a material is defined as: EQU K=.epsilon./.epsilon..sub.0
While decreasing the thickness of the gate dielectric effectuates increased capacitive coupling between two conductive layers, it has several disadvantages. For instance, relatively thin gate dielectrics tend to break down when subjected to an electric field. Electrons may pass through the thin gate dielectric by what is known as the quantum mechanical tunneling effect. As a result, a tunneling current may inadvertently flow between the two conductive layers. On the other hand, a dielectric having a relatively high K value may be formed to a greater thickness and still provide for the same amount of capacitance as a thinner dielectric having a lower K value. Accordingly, dielectrics having relatively high K values are growing in popularity for use as gate dielectrics in integrated circuit devices.
Metal oxides which have high K values (e.g., K&gt;8.0), such as tantalum pentoxide, may be used as the gate dielectric. The metal oxide is typically formed using chemical-vapor deposition ("CVD"). Unfortunately, a CVD deposited metal oxide is typically not stoichiometric and contains oxygen vacancies. For example, Ta.sub.2 O.sub.5 formed by the CVD method may contain molecules having 3 or 4 oxygen atoms instead of 5 oxygen atoms. Absent the appropriate number of oxygen atoms, molecules within the metal oxide may include dangling bonds to which foreign atoms can undesirably bond. Further, the oxygen vacancies within the metal oxide may provide migration pathways through the gate dielectric. Foreign atoms may thus pass through the gate dielectric between the overlying and underlying conductive layers. For example, dopants residing within an overlying gate conductor may be able to diffuse through the gate dielectric to an underlying semiconductor substrate where they can render the device inoperable. The vacancies in the gate dielectric also function as carrier-bodies for leakage current, and thereby cause the gate dielectric to have a low breakdown voltage. Moreover, the oxygen vacancies may serve as traps for hot carriers (e.g., electrons) injected into the gate dielectric. As the trapped charge accumulates over time, the capacitance of a device employing the gate dielectric may unfortunately shift from its design specification.
It would therefore be of benefit to develop a high K gate dielectric which experiences little current leakage and has a high breakdown voltage. That is, a gate dielectric is needed which provides for high capacitive coupling between two conductive layers separated by the gate dielectric while also having a low breakdown voltage. Further, it would be desirable to form a gate dielectric in which hot carrier entrapment is less likely to occur. Moreover, the migration of species through the gate dielectric must be prevented to ensure that foreign species do not enter the overlying and underlying conductive layers. In particular, the amount of oxygen vacancies within the gate dielectric needs to be reduced to prevent hot carrier entrapment and current leakage in the gate dielectric, and to prevent the diffusion of species through the gate dielectric.